@article{FOM+5,
title = { A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits },
author = {Ferres, Bruno and Oulkaid, Oussama and Moy, Matthieu and Radanne, Gabriel and Henrio, Ludovic and Raymond, Pascal and Khosravian, Mehdi},
month = {jul},
year = {2025},
address = {New York, NY, USA},
note = {Just Accepted},
journal = {ACM Trans. Des. Autom. Electron. Syst.},
publisher = {Association for Computing Machinery},
team = {SYNC},
abstract = {Hardware verification is crucial to ensure the quality of Integrated Circuits, and prevent costly bugs down the manufacturing flow. Electrical Rule Checking (ERC) is a verification step used to assert that a circuit complies with some electrical rules, from the absence of short-circuits to dedicated constructor rules. In this survey, we provide a global overview of existing ERC techniques at transistor-level, where voltage values are explicit. We propose a new classification method to compare the existing approaches based on their semantic modeling of circuits. This survey precisely describes transistor-level ERC research challenges and existing solutions. We believe it will help structure this research domain by positioning existing approaches with respect to each other. Obviously, a survey should also facilitate technological transfer and this one should help CAD vendors identify the most relevant approaches to integrate in their tools. Finally, we highlight several promising directions to improve the existing solutions.},
}
