Home
>
Archives
>
Synchrone (Archive)
>
Synchrone Research Topics
>
Virtual Prototyping and Simulation
xxx
Browsing
Sections
Verimag
Topics
Contact
Site Map
Building Access
News
Seminars
Seminars
11 December 2025
Thaïs Baudon:
Compiling types and other high-level language features for performance or security
18 December 2025
Jérémie Decouchant:
A venir (theme cybersecu)
New publications
Some Recent Publications
Marius Bozga, Radu Iosif, Arnaud Sangnier, Neven Villani:
Counting Abstraction and Decidability for the Verification of Structured Parameterized Networks
Bruno Ferres, Oussama Oulkaid, Matthieu Moy, Gabriel Radanne, Ludovic Henrio, Pascal Raymond, Mehdi Khosravian:
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits
Akram Idani, Yves Ledru, German Vega:
Formal model-driven security combining B-method and process algebra: The B4MSecure platform
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing synchronous unison in directed networks
Jobs and internships
Jobs and internships
[Funded PhD] Fault Injection Attacks: Automated Analysis of Counter-Measures At The Binary Level
[Master] Decision Procedure for Equivalence Relations
[Master]Leakage in presence of an active and adaptive adversary
[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
Contact
|
Site Map
|
Site powered by SPIP 4.4.5
+
AHUNTSIC
[CC License]
info visites
5201559
English
Français